Enhancing semiconductor device performance and increasing device density (the number of devices per unit area), continue to be important objectives of the semiconductor industry. Device density is increased by making individual devices smaller and packing devices more compactly. But, as the device dimensions (also referred to as the feature size or design rules) decrease, the methods for forming devices and their constituent elements must be adapted. For instance, production device sizes are currently in the range of 0.25 microns to 0.18 microns, with an inexorable trend toward smaller dimensions. However, as the device dimensions shrink, certain manufacturing limitations arise, especially with respect to the lithographic processes. In fact, current lithographic processes are nearing the point where they are unable to accurately manufacture devices at the required minimal sizes demanded by today's device users.
Currently most metal-oxide-semiconductor field effect transistors (MOSFETs) are formed in a lateral configuration, with the current flowing parallel to the plane of the substrate or body surface. As the size of these MOSFET devices decreases to achieve increased device density, the fabrication process becomes increasingly difficult. In particular, the lithographic process for creating the gate channel is problematic, as the wavelength of the radiation used to delineate an image in the lithographic pattern approaches the device dimensions. Therefore, for lateral MOSFETs, the gate length is approaching the point where it cannot be precisely controlled through the lithographic techniques.
Recent advances in packing density have resulted in several variations of a vertical MOSFET. In particular, the vertical device described in Takato, H., et al., “Impact of Surrounding Gates Transistor (SGT) for Ultra-High-Density LSI's, IEEE Transactions on Electron Devices, Volume 38(3), pp. 573–577 (1991), has been proposed as an alternative to the planar MOSFET devices. Recently, there has been described a MOSFET characterized as a vertical replacement gate transistor. See Hergenrother, et al, “The Vertical-Replacement Gate (VRG) MOSFET” A50-nm Vertical MOSFET with Lithography-Independent Gate Length,” Technical Digest of the International Electron Devices Meeting, p. 75, 1999.
A plurality of planar MOSFET active devices fabricated on an integrated circuit chip are shown in the FIG. 1 cross-sectional view. A substrate 9 comprises a p+ region 50 and a p− layer 52, the latter typically grown by an epitaxial technique. MOSFETs (metal-oxide-semiconductor field-effect transistor) 2, 4 and 6 are fabricated in the substrate 9. The MOSFET 2 is separated from the MOSFET 4 by a LOCOS (local oxidation on silicon substrate) region 10. Similarly, the MOSFET 6 is separated from the MOSFET 4 by a LOCOS region 12. Alternatively, the MOSFETS 2, 4 and 6 may be electrically separated by shallow trench isolation (STI) techniques. The MOSFET 2 includes a gate 14 and a source region 16 and a drain region 18 diffused in an n-type well 20. The MOSFET 4 includes a gate 28 and a source region 30 and a drain region 32 diffused in a p-type well 34. Finally, the MOSFET 6 includes a gate 38 and a source region 40 and a drain region 42 diffused in an n-type well 44. The gates 14, 28 and 38 are separated from the substrate 9 by a silicon dioxide layer 46, also referred to as a gate oxide layer. As FIG. 1 is intended to be a simplified representation of a portion of an integrated circuit, the various contacts, interconnects, vias and metal layers are not shown and the features are not drawn to scale. It is particularly advantageous, especially in digital applications, to fabricate a combination of an n-channel and a p-channel MOSFETs on adjacent regions of a chip. This complementary MOSFET (CMOS) configuration is illustrated in the form of a basic inverter circuit in FIG. 2. The drains of the MOSFETs (for instance the MOSFETs 2 and 4 in FIG. 1) are connected together and form the output (Vout). The input terminal (Vin) is formed by the common connection of the MOSFET gates (for example the gates 14 and 28 of FIG. 1). The operating voltage is designated by VDD. In the FIG. 2 schematic, the MOSFET 2 is the PMOS device and the MOSFET 4 is the NMOS device illustrated in the FIG. 1 cross-section.
State-of-the-art integrated circuit fabrication combines many different functions and subsystems onto a single chip, for example, combining different types of logic circuits, logic families and memory elements. For optimal performance and minimal power consumption individual devices on the integrated circuit may operate at different voltages. Thus, the active devices must be fabricated with the necessary physical characteristics to accommodate the selected operating voltage. But in creating these physical device characteristics, it is also desirable to minimize and simplify the number of fabrication process steps.
For example, each of the MOSFETs 2, 4 and 6 of FIG. 1, may be designed to operate at a different operating voltage, i.e., Vdd/VSS. It is desired to establish the device operating voltage at the minimum value that provides the desired performance to minimize the power consumption of the devices, and overall, the power consumption of the chip. It is known, however, that there is a counter-effect; as the device operating voltage is reduced the operating speed of the device is also reduced. Therefore, to establish the optimum value for both of these parameters, it is necessary to operate the individual devices at operating voltages consistent with the desired speed performance. To provide multiple operating voltages, a printed circuit board carrying several integrated circuits includes multiple voltage regulators to supply the optimum operating voltage to each chip. Further, an individual chip may include on-chip voltage divider and regulator circuits so that the devices within the chip are supplied with the optimum operating voltage.
Given that there may be multiple operating voltages on a chip, there may also be multiple output voltages produced by the active elements and circuits of the chip. Thus the input circuit or device responsive to the preceding output voltage must be able to accommodate that output voltage. For example, a first on-chip circuit (which may comprise a single active element or a plurality of active elements, such as a CMOS circuit) has an output voltage ranging from zero volts to two volts, representing, respectively, a binary zero and a binary one. The output voltage of another circuit element is zero volts for a binary zero and five volts for a binary one. Therefore, the MOSFET gate terminal (the input terminal of the MOSFET device) must be designed to accommodate the voltage range of the output signal from the previous device in the circuit chain. Thus, returning to the above example, certain MOSFET gate voltages must accommodate a voltage range of zero to two volts, while others must accommodate a voltage range of zero to five volts. Once the gate driving voltage is known, the MOSFET gate must be designed and fabricated to ensure that the gate can withstand that voltage. Thus, MOSFETs operating at higher gate voltages will have thicker oxides to prevent gate oxide breakdown at the higher operating voltages. Since the gate oxide thickness effects the threshold voltage, it is also necessary to ensure that the MOSFET will be driven into conduction by the gate input voltage. This can be accomplished by adjusting the other factors that influence the threshold voltage, such as the doping level of the channel region and the work function of the channel and gate materials.
One technique for varying the thickness of oxide growth involves nitrogen implantation in the material to be oxidized. See for example the article entitled “High Performance 0.2 μm CMOS with 25 Angstroms Gate Oxide Grown on Nitrogen Implanted Silicon Substrates,” by C. T. Liu, et al, IEDM, 1996, pp. 499–502. As is known, nitrogen implantation before a thermal oxide growth process results in inhibition of the oxide growth. Large nitrogen dosages produce thin oxides. This process is not applicable to a MOSFET constructed according to the teachings of the present invention because acceptable access cannot be gained to the region where the gate is formed to implant the nitrogen.